Power overlay structure and method of making same

ABSTRACT

A power overlay (POL) structure includes a POL sub-module. The POL sub-module includes a dielectric layer and a semiconductor device having a top surface attached to the dielectric layer. The top surface of the semiconductor device has at least one contact pad formed thereon. The POL sub-module also includes a metal interconnect structure that extends through the dielectric layer and is electrically coupled to the at least one contact pad of the semiconductor device. A conducting shim is coupled to a bottom surface of the semiconductor device and a first side of a thermal interface is coupled to the conducting shim. A heat sink is coupled to a second side of the electrically insulating thermal interface.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a continuation of and claims priority to U.S.Non-Provisional patent application Ser. No. 14/665,735 filed Mar. 23,2015, which is a continuation of and claims priority to U.S.Non-Provisional patent application Ser. No. 13/897,638 filed May 20,2013, now U.S. Pat. No. 8,987,876, which claims priority to U.S.Provisional Patent Application Ser. No. 61/784,834 filed Mar. 14, 2013,the disclosures of which are incorporated herein by reference in theirentireties.

BACKGROUND OF THE INVENTION

Embodiments of the invention relate generally to structures and methodsfor packaging semiconductor devices and, more particularly, to a poweroverlay (POL) packaging structure that includes an improved thermalinterface.

Power semiconductor devices are semiconductor devices used as switchesor rectifiers in power electronic circuits, such as switched mode powersupplies, for example. Most power semiconductor devices are only used incommutation mode (i.e., they are either on or off), and are thereforeoptimized for this. Many power semiconductor devices are used in highvoltage power applications and are designed to carry a large amount ofcurrent and support a large voltage. In use, high voltage powersemiconductor devices are connected to an external circuit by way of apower overlay (POL) packaging and interconnect system.

The general structure of a prior art power overlay (POL) structure 10 isshown in FIG. 1. The standard manufacturing process for the POLstructure 10 typically begins with placement of one or more powersemiconductor devices 12 onto a dielectric layer 14 by way of anadhesive 16. Metal interconnects 18 (e.g., copper interconnects) arethen electroplated onto dielectric layer 14 to form a direct metallicconnection to the power semiconductor devices 12. The metalinterconnects 18 may be in the form of a low profile (e.g., less than200 micrometers thick), planar interconnect structure that provides forformation of an input/output (I/O) system 20 to and from the powersemiconductor devices 12. For connecting to an external circuit, such asby making a second level interconnection to a printed circuit board forexample, current POL packages use solder ball grid arrays (BGAs) or landgrid arrays (LGAs).

A heat sink 22 is also typically included in the POL structure 10 toproviding a way to remove the heat generated by semiconductor devices 12and protect the devices 12 from the external environment. Heat sink 22is thermally coupled to the devices 12 using a direct bond copper (DBC)substrate 24. As shown, DBC substrate 24 is positioned between the uppersurfaces of semiconductor devices 12 and the lower surface of heat sink22.

DBC substrate 24 is a prefabricated component that includes anon-organic ceramic substrate 26 such as, for example, alumina, withupper and lower sheets of copper 28, 30 bonded to both sides thereof viaa direct bond copper interface or braze layer 31. The lower copper sheet30 of DBC substrate 24 is patterned to form a number of conductivecontact areas before DBC substrate 24 is attached to semiconductordevices 12. A typically DBC substrate may have an overall thickness ofapproximately 1 mm.

During the fabrication process of POL structure 10, solder 32 is appliedto the surfaces of semiconductor devices 12. DBC substrate 24 is thenlowered onto solder 32 to align the patterned portions of lower coppersheet 30 with solder 32. After DBC substrate 24 is coupled tosemiconductor devices 12, an underfill technique is used to apply adielectric organic material 34 in the space between adhesive layer 16and DBC substrate 24 to form a POL sub-module 36. A thermal pad orthermal grease 38 is then applied to the upper copper layer 28 of DBCsubstrate 24.

The use of a DBC substrate in a POL structure 10 has a number oflimitations. First, the material properties of the copper and ceramicmaterials of the DBC substrate place inherent limitations on the designof the DBC substrate. For example, due to the inherent stiffness ofceramics and the differences in the thermal expansion coefficients ofthe copper and ceramic materials of DBC substrate 24, copper sheets 28,30 must be kept relatively thin to avoid undue stresses placed on theceramics caused by large swings in temperature in the copper material.In addition, since the surface of the lower copper layer of the DBCsubstrate 24 that faces semiconductor device(s) 12 is planar, the DBCsubstrate 24 does not facilitate fabrication of a POL package havingsemiconductor devices of differing height.

Also, DBC substrates are relatively expensive to manufacture and are aprefabricated component. As DBC substrate 24 is a prefabricatedcomponent, the thickness of copper sheets 28, 30 is predetermined basedon the thickness of the copper foil layer applied to the ceramicsubstrate 26. Also, because DBC substrate 24 is fabricated prior toassembly with the remainder of the components of the POL structure, thedielectric filler or epoxy substrate that surrounds the semiconductordevices 12 is applied using an underfill technique after the DBCsubstrate 24 is coupled to semiconductor devices 12. This underfilltechnique is time consuming and can result in undesirable voids withinthe POL structure.

Therefore, it would be desirable to provide a POL structure having animproved thermal interface that overcomes the aforementioned structuraland processing limitations of known POL structures that incorporate aDBC substrate. It would further be desirable for such a POL structure toaccount for semiconductor devices of different thickness whileminimizing cost of the POL structure.

BRIEF DESCRIPTION OF THE INVENTION

Embodiments of the invention overcome the aforementioned drawbacks byproviding a power overlay (POL) structure that eliminates the usage of aDBC substrate as a thermal interface between a POL sub-module and a heatsink. An improved thermal interface is provided between semiconductordevices and the heat sink that includes conducting shims that accountfor semiconductor devices of varying heights.

In accordance with one aspect of the invention, a power overlay (POL)structure includes a POL sub-module. The POL sub-module includes adielectric layer and a semiconductor device having a top surfaceattached to the dielectric layer. The top surface of the semiconductordevice has at least one contact pad formed thereon. The POL sub-modulealso includes a metal interconnect structure that extends through thedielectric layer and is electrically coupled to the at least one contactpad of the semiconductor device. A conducting shim is coupled to abottom surface of the semiconductor device and a first side of a thermalinterface is coupled to the conducting shim. A heat sink is coupled to asecond side of the electrically insulating thermal interface.

In accordance with another aspect of the invention, a method of forminga power overlay (POL) structure includes providing a semiconductordevice, affixing a first surface of the semiconductor device to adielectric layer, forming vias through the dielectric layer and forminga metal interconnect structure extending through the vias in thedielectric layer to electrically connect to the semiconductor device.The method also includes affixing a first surface of a conductive shimto a second surface of the semiconductor device and forming a thermalinterface atop a second surface of the conductive shim. Further, themethod includes thermally coupling a heat sink to the conductive shimabsent a direct bond copper (DBC) substrate positioned between the heatsink and the conductive shim.

In accordance with yet another aspect of the invention, a power overlay(POL) packaging structure includes a POL sub-module. The POL sub-moduleincludes a dielectric layer, a first semiconductor device attached tothe dielectric layer, and an interconnect structure electrically coupledto a first side of the first semiconductor device. The interconnectstructure extends through the dielectric layer to electrically connectto at least one contact pad on the first semiconductor device. A firstconducting shim has a bottom surface coupled to a second side of thefirst semiconductor device and a thermal interface coupled to a topsurface of the first conducting shim absent a direct bond copper (DBC)substrate positioned therebetween. A heat sink is directly coupled tothe thermal interface.

In accordance with yet another aspect of the invention, a semiconductordevice package includes a first semiconductor device, a secondsemiconductor device having a thickness that is greater than a thicknessof the first semiconductor device, and an insulating substrate coupledto first surfaces of the first and second semiconductor devices. Ametallization layer extends through the insulating substrate such that afirst surface of the metallization layer is coupled to the contact padsof the first and second semiconductor devices. A first conducting shimhaving a first side is coupled to the first semiconductor device via aconductive contact layer; a second conducting shim having a first sideis coupled to the first semiconductor device via the conductive contactlayer. The first conducting shim has a thickness that is greater than athickness of the second conducting shim and second sides of the firstand second conducting shims are co-planar.

In accordance with yet another aspect of the invention, a semiconductordevice package includes a dielectric layer having a plurality of viasformed therethrough and a semiconductor device having a first surfacecoupled to a top surface of the dielectric layer. The semiconductordevice package also includes a metal interconnect structure coupled to abottom surface of the dielectric layer. The metal interconnect structureextends through the plurality of vias of the dielectric layer to connectto the first surface of the semiconductor device. The semiconductordevice package also includes a conducting shim having a bottom surfacecoupled to a second surface of the semiconductor device and an organicthermal interface coupled to a top surface of the conducting shim absenta direct bond copper (DBC) substrate positioned between the organicthermal interface and the conducting shim.

These and other advantages and features will be more readily understoodfrom the following detailed description of preferred embodiments of theinvention that is provided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings illustrate embodiments presently contemplated for carryingout the invention.

In the drawings:

FIG. 1 is a schematic cross-sectional side view of a prior art poweroverlay (POL) structure incorporating a DBC substrate.

FIG. 2 is a schematic cross-sectional side view of a POL structureaccording to an embodiment of the invention.

FIG. 3 is a schematic cross-sectional side view of a POL structureaccording to another embodiment of the invention.

FIG. 4 is a schematic cross-sectional side view of a POL structureaccording to yet another embodiment of the invention.

FIG. 5 is a schematic cross-sectional side view of a POL assemblyaccording to an embodiment of the invention.

FIGS. 6-16 are schematic cross-sectional side views of a POL sub-moduleduring various stages of a manufacturing/build-up process according toembodiments of the invention.

FIG. 17 is a schematic cross-sectional side view of a portion of aleaded POL sub-module according to another embodiment of the invention.

FIG. 18 is a schematic cross-sectional side view of a portion of aleaded POL sub-module according to another embodiment of the invention.

FIG. 19 is a schematic cross-sectional side view of a portion of a POLsub-module having a stepped conducting shim according to an embodimentof the invention.

FIG. 20 is a schematic cross-sectional side view of a portion of a POLsub-module having a multi-layer conducting shim assembly according to anembodiment of the invention.

DETAILED DESCRIPTION

Embodiments of the present invention provide for a power overlay (POL)structure having an improved thermal interface included therein, as wellas a method of forming such a POL structure. The POL structure includesconducting shims that account for semiconductor devices of varyingheights and a thermal interface layer that increases options forencapsulation materials and methods.

Referring to FIG. 2, a semiconductor device assembly or power overlay(POL) structure 40 is shown according to an embodiment of the invention.POL structure 40 includes a POL sub-module 42 having one or moresemiconductor devices 43, 44, 45 therein that, according to variousembodiments, may be in the form of a die, diode, or other power electricdevice. As shown in FIG. 2, three semiconductor devices 43, 44, 45 areprovided in POL sub-module 42, however, it is recognized that a greateror lesser number of semiconductor devices 43, 44, 45 could be includedin POL sub-module 42. In addition to semiconductor devices 43, 44, 45,POL sub-module 42 may also include any number of additional circuitrycomponents 46 such as, for example, a gate driver.

Semiconductor devices 43, 44, 45 are coupled to a dielectric layer 48 byway of an adhesive layer 50. Dielectric layer 48 may be in the form of alamination or a film, according to various embodiments, and may beformed of one a plurality of dielectric materials, such as Kapton®,Ultem®, polytetrafluoroethylene (PTFE), Upilex®, polysulfone materials(e.g., Udel®, Radel®), or another polymer film, such as a liquid crystalpolymer (LCP) or a polyimide material.

POL sub-module 42 also includes a metallization layer or interconnectstructure 52, which forms a direct metallic connection to semiconductordevices 43, 44, 45 by way of a metal interconnects 54 that extendsthrough vias 56 formed in dielectric layer 48 to connect to contact pads58 on respective semiconductor devices 43, 44, 45.

POL sub-module 42 further includes one or more conducting slabs or shims60, which are secured to semiconductor devices 43, 44, 45 with athermally and electrically conductive contact layer 62. According tovarious embodiments, conductive contact layer 62 may be a soldermaterial, a conductive adhesive, or a sintered silver, as examples.Conducting shims 60 are a metal or alloy material, such as, for example,copper, aluminum, molybdenum, or combinations thereof such ascopper-molybdenum or copper-tungsten, and composites such asaluminum-silicon, aluminum-silicon carbide, aluminum-graphite,copper-graphite and the like.

A dielectric filler material 64 is also provided in POL sub-module 42 tofill gaps in the POL sub-module 42 between and around semiconductordevices 43, 44, 45 and conducting shims 60, so as to provide additionalstructural integrity to POL sub-module 42. According to variousembodiments, dielectric filler material 64 may be in the form of apolymeric material, such as, for example, an underfill (e.g., capillaryunderfill or no-flow underfill), encapsulate, silicone, or a moldingcompound.

POL structure 40 also includes a heat sink 66 to facilitate cooling ofsemiconductor devices 43, 44, 45. Heat sink 66 comprises a materialhaving a high thermal conductivity, such as copper, aluminum, or acomposite material. Heat sink 66 is coupled to POL sub-module 42 by wayof a thermal interface substrate or layer 68 formed over conductingshims 60 and dielectric filler material 64.

Thermal interface layer 68 is a thermally conductive, electricallyinsulating polymeric or organic material such as, for example, a thermalpad, a thermal paste, a thermal grease, or a thermal adhesive. Thermalinterface layer 68 electrically isolates heat sink 66 from conductingshims 60. According to one embodiment, thermal interface layer 68comprises conductive fillers, particles, or fibers suspended in a matrixof resin or epoxy. For example, thermal interface layer 68 may be anepoxy or silicon resin that is filled with thermally conductive,electrically insulating fillers such as alumina and/or boron nitride.According to one embodiment, thermal interface layer 68 has a thicknessof approximately 100 μm. However, one skilled in the art will recognizethat the thickness of thermal interface layer 68 may vary based ondesign specifications. Thermal interface layer 68 provides superiorthermal performance as compared to a DBC substrate because thermalinterface layer 68 is not subject to the thermal resistance of theceramic layer included within DBC substrate.

In embodiments where thermal interface layer 68 is a thermal paste, athermal grease, or a thermal pad, such as, for example a pre-formedsheet or film of organic material, heat sink 66 is secured to POLsub-module 42 using screws or other fastening devices (not shown), at anumber of locations around the perimeter of POL sub-module 42 causingthermal interface layer 68 to be sandwiched between conducting shims 60and heat sink 66. Alternatively, in embodiments where thermal interfacelayer 68 is a polymeric adhesive, thermal interface layer 68 is appliedto POL sub-module 42 in a tacky state and cured after heat sink 66 ispositioned atop thermal interface layer 68, thereby bonding heat sink 66to POL sub-module 42 absent additional fasteners.

POL sub-module 42 also includes an input-output (I/O) connection 70 toenable surface mounting of the POL structure 40 to an external circuit,such as a printed circuit board (PCB), as described in more detail withrespect to FIG. 5. According to an exemplary embodiment, I/O connection70 is formed of ball grid array (BGA) solder bumps 72 that areconfigured to be attached/affixed to the PCB to electrically couple POLstructure 40 to the PCB, although other suitable second-level solderinterconnections, such as land grid array (LGA) pads, could also beused. The BGA solder bumps 72 provide a highly reliable interconnectionstructure that is resistive to failure in high stress conditions. Asillustrated in FIG. 2, solder bumps 72 are positioned in openings formedin a solder mask layer 74 of POL sub-module 42.

Referring now to FIG. 3, a POL structure 76 and POL sub-module 78 areshown according an alternative embodiment of the invention. POLstructure 76 and POL sub-module 78 include a number of componentssimilar to components shown in POL structure 40 and POL sub-module 42 ofFIG. 2, and thus numbers used to indicate components in FIG. 2 will alsobe used to indicate similar components in FIG. 3.

As shown, POL sub-module 78 includes a multi-layer thermal interface 80positioned between conducting shims 60 and heat sink 66. Multi-layerthermal interface 80 includes a first thermal interface layer 82, aceramic insulator layer 84, and a second thermal interface layer 86. Theinclusion of ceramic insulator layer 84 between POL sub-module 78 andheat sink 66 provides additional electrical isolation for high voltageapplications. Insulator layer 84 may be constructed of a ceramicmaterial such as alumina or aluminum nitride, as examples.

As shown, first thermal interface layer 82 is sandwiched betweenconducting shims 60 and ceramic insulator layer 84. According to oneembodiment first thermal interface layer 82 of FIG. 3 comprises athermally conductive, electrically insulating material similar tothermal interface layer 68 of FIG. 2 that permits the transfer of heatfrom conducting shims 60 to heat sink 66 while electrically isolatingconducting shims 60 from heat sink 66. In an exemplary embodiment, firstthermal interface layer 82 comprises an epoxy or silicon resin that isfilled with thermally conductive but electrically insulating fillerssuch as alumina or boron nitride.

In an alternative embodiment, first thermal interface layer 82 comprisesan electrically conductive material, such as, for example, solder,conductive adhesive, or sintered silver, formed as a number of discretepads 88 atop conducting shims 60, as illustrated in FIG. 4. Lateralspaces 90 between adjoining pads 88 may be left as air gaps or be filledwith dielectric filler material 64, according to various embodiments.

Referring now to FIG. 3 and FIG. 4 together, second thermal interfacelayer 86 is sandwiched between ceramic insulator layer 84 and heat sink66. According to one embodiment, second thermal interface layer 86comprises a thermally conductive, electrically insulating materialsimilar to thermal interface layer 68 of FIG. 2. In an alternativeembodiment, second thermal interface layer 86 is a material that is boththermally and electrically conductive, such as, for example, an epoxy orsilicon resin filled with silver.

FIG. 5 illustrates a POL assembly 92 incorporating POL structure 40(FIG. 2) and POL structure 76 (FIGS. 3, 4) in accordance with anembodiment of the invention. As shown, respective I/O connections 70 ofPOL structures 40, 76 are coupled to an external circuit component 94,such as, for example, a printed circuit board (PCB). While two POLstructures 40, 76 are illustrated in POL assembly 92, one skilled in theart will recognize that POL assembly 92 may include any number of POLstructures, according to various embodiments of the invention. Further,POL assembly 92 may include multiple POL structures of a single type,such as two or more POL structures 40 or two or more POL structures 76.

Referring now to FIGS. 6-16, detailed views of the process steps for atechnique of manufacturing POL sub-module 42 of FIG. 2 and POLsub-module 78 of FIGS. 3 and 4 are provided, according to an embodimentof the invention. Referring first to FIG. 6, the build-up process of POLsub-module 42, 78 begins with applying an adhesive layer 50 ontodielectric layer 48. In a next step of the technique, one or moresemiconductor device(s) 44, 45 (e.g., two semiconductor devices) aresecured to dielectric layer 48 by way of adhesive layer 50, asillustrated in FIG. 7. To secure the semiconductor devices 44, 45 todielectric layer 48, the top surfaces 96 of semiconductor devices 44, 45are placed onto adhesive layer 50. Adhesive 50 is then cured to securesemiconductor devices 44, 45 onto dielectric layer 48.

A plurality of vias 56 is then formed through adhesive layer 50 anddielectric layer 48, as illustrated in FIG. 8. According to embodimentsof the invention, vias 56 may be formed by way of a laser ablation orlaser drilling process, plasma etching, photo-definition, or mechanicaldrilling processes.

While the formation of vias 56 through adhesive layer 50 and dielectriclayer 48 is shown in FIG. 8 as being performed after placement ofsemiconductor devices 44, 45 onto adhesive layer 50, it is recognizedthat the placement of semiconductor devices 44, 45 could occur after tovia formation. Alternately, depending on constraints imposed by viasize, semiconductor devices 44, 45 could first be placed on adhesivelayer 50 and dielectric layer 48, with the vias 56 subsequently beingformed at locations corresponding to a plurality of metalized circuitsand/or connection pads or contact pads 58 formed on semiconductordevices 44, 45. Furthermore, a combination of pre- and post-drilled viascould be employed.

Referring now to FIGS. 9 and 10, upon securing of semiconductor devices44, 45 on the dielectric layer 48 and the formation of vias 56, the vias56 are cleaned (such as through a reactive ion etching (RIE) desootprocess) and subsequently metalized to form a metallization orinterconnection layer 54. Metallization layer 54 is typically formedthrough a combination of sputtering and electroplating applications,although it is recognized that other electroless methods of metaldeposition could also be used. For example, a titanium adhesion layerand copper seed layer may first be applied via a sputtering process,followed by an electroplating process that increases a thickness of thecopper to a desired level. The applied metal material is thensubsequently patterned into metal interconnects 54 having a desiredshape and that function as vertical feed-throughs formed throughdielectric layer 48 and adhesive layer 50. Metal interconnects 54 extendout from circuits and/or connection pads or contact pads 58 ofsemiconductor devices 44, 45, through vias/opening 56, and out across atop surface 98 of dielectric layer 48.

As shown in FIG. 11, a solder mask layer 74 is applied over thepatterned metal interconnects 54 to provide a protective coating anddefine interconnect pads. In an alternative embodiment, it is recognizedthat that the interconnect pads can have a metal finish to aidsolderability, such as Ni or Ni/Au.

Referring now to FIG. 12, in a next step of the fabrication technique, aconductive contact layer 62 is applied to a bottom surface 100 ofsemiconductor devices 44, 45. A bottom surface 102 of conducting shims60 are then coupled to semiconductor device 44, 45 by way of theconductive contact layer 62.

According to one embodiment of the invention, and as shown in FIG. 12,semiconductor devices 44, 45 may be of varying thickness/height. Inorder to equalize the overall height of respective semiconductor devices44, 45, conducting shims 60 may be of differing height so that theoverall thickness/height of each semiconductor devices 44, 45/conductingshim pair 60 is equal and a back surface of the conducting shims 60 is“planarized.”

As shown in FIG. 13, the build-up technique of manufacturing POLsub-module 42, 78 continues with the application of a dielectric fillermaterial 64 to fill in gaps in POL sub-module 42, 78 between and aroundsemiconductor devices 44, 45 and conducting shims 60, so as to constraindielectric layer 48 and provide additional electrical insulation andstructural integrity to POL sub-module 42, 78. In one embodiment,dielectric filler material 64 is applied using an overmolding techniqueand cured. After dielectric filler material 64 is cured, a portion 104of dielectric filler material 64 is removed using a grinding operationto expose conducting shim 60. This grinding operation may also be usedto remove any variation in the height of conducting shims 60 so that atop surface 106 of conducting shims 60 and a top surface top surface 108of dielectric filler material 64 is coplanar, as shown in FIG. 14.Alternatively, an overmolding or encapsulating technique may be used toapply dielectric filler material 64 such that the top surface 108 of thecured dielectric filler material 64 is flush with the top surface 106 ofconducting shims 60 absent a grinding step. In yet another embodiment,dielectric filler material 64 may be applied using an underfilltechnique.

In a next step of the fabrication process, a first side 110 of a thermalinterface 112 is applied to respective top surfaces 106, 108 ofconducting shims 60 and dielectric filler material 64, as shown in FIG.15. In embodiments where thermal interface 112 comprises single thermalinterface layer 68 (FIG. 2), thermal interface 112 is applied in onestep to the top surfaces 106, 108 of conducting shims 60 and dielectricfiller material 64. Alternatively, thermal interface 112 may be amulti-layer thermal interface 80 as shown in FIGS. 3 and 4. Referring aswell to FIGS. 3 and 4, the individual layers of multi-layer thermalinterface 80 are applied sequentially to the top surfaces 106, 108 ofconducting shims 60 and dielectric filler material 64 using a build-uptechnique wherein first thermal interface layer 82 is applied atopdielectric filler material 64 and conducting shims 60, ceramic insulatorlayer 84 is next applied atop first thermal interface layer 82, andsecond thermal interface layer 86 is finally applied to the top surfaceof ceramic insulator layer 84.

In a next step of the fabrication technique, I/O connections 70 areapplied to solder mask layer 74. In one embodiment, I/O connections 70are solder bumps 72, as shown in FIG. 16. In an alternative embodimentof the build-up technique, I/O connections 70 are configured as leads114 for a through-hole component, as shown in FIG. 17. After thebuild-up process of POL sub-module 42, 78 is complete, a heat sink 66 isaffixed to a second side 116 of thermal interface 112. POL sub-module42, 78 may be singulated for surface mounting to an external circuit,such as PCB 94 (FIG. 5).

Referring now to FIG. 18, an alternative embodiment of a POL sub-module118 is illustrated. POL sub-module 118 includes a number of componentssimilar to components shown in POL sub-module 42 of FIG. 2, and thusnumbers used to indicate components in FIG. 2 will also be used toindicate similar components in FIG. 18.

As shown, POL sub-module 118 includes semiconductor device(s) 44 mountedto a dielectric layer 48 by way of an adhesive layer 50. Metalinterconnects 54 extend through vias 56 formed in dielectric layer 48 toconnect to contact pads (not shown) on semiconductor device(s) 44. Aconducting shim 120 is coupled to each semiconductor device 44 by way ofa conductive contact layer 62. Similar to conducting shims 60 of FIG. 2,conducting shims 120 comprise a metal or alloy material, such as, forexample, copper, aluminum, molybdenum, or combinations thereof.Dielectric filler material 64 is provided to fill gaps in POL sub-module118 between and around semiconductor devices 44 and conducting shims120. A thermal interface 112, such as thermal interface layer 68 (FIG.2) or multi-layer thermal interface 80 (FIG. 3), is provided atopdielectric filler material 64 and conducting shims 120.

As shown in FIG. 18, conducting shims 120 are coupled to a lead-frame122. According to embodiments of the invention, lead-frame 122 ispre-attached to conducting shim 120 prior to placement of conductingshims 120 into conductive contact layer 62. For example, lead-frame 122and conducting shims 60 may be a pre-fabricated from a common copperslab or lead-frame 122 may be pre-attached to conducting shims 60 by wayof a high temperature joining process like soldering, brazing, welding,or other similar method for assembly into POL sub-module 118.Alternatively, it is recognized that lead-frame 122 may be post-attachedinstead, after fabrication of POL sub-module 118 is completed.

Referring now to FIGS. 19 and 20, two alternative embodiments of a POLsub-module 124 are illustrated that account for situations wherein POLsub-module 124 includes semiconductor devices 126, 128 of differingheights. Again, as POL sub-module 124 includes a number of componentssimilar to components shown in POL sub-module 42 of FIG. 2, and thusnumbers used to indicate components in FIG. 2 will also be used toindicate similar components in FIGS. 19 and 20.

Referring first to FIG. 19, an alternative embodiment is shown thatincludes a conducting shim 130 having a stepped configuration. As shown,a first portion 132 of conducting shim 130 has a first height orthickness 134 and a second portion 136 of conducting shim 130 has asecond height or thickness 138 to account for the differing heights ofsemiconductor devices 126, 128 while maintaining a planar top surface140 of conducting shim 130.

An alternative embodiment of POL sub-module 124 is shown in FIG. 20,wherein a first conducting shim 142 is coupled to semiconductor device126 using a first conductive contact layer 144, such as, for example, asolder similar to conductive contact layer 62 (FIG. 2). First conductingshim 142 is sized such that an upper surface 146 of first conductingshim 142 and an upper surface 148 of semiconductor device 128 arecoplanar. A second conductive contact layer 150 is then applied to thetop surfaces of first conducting shim 142 and semiconductor device 128.In one embodiment, second conductive contact layer 150 comprises solder.A second conducting shim 152, which is sized to span at least theoverall width of semiconductor devices 126, 128 is then affixed tosecond conducting shim 152 as shown.

Beneficially, embodiments of the invention thus provide a POL packagingand interconnect structure that includes a thermal interface that isabsent the drawbacks of a DBC substrate. For example, as thermalinterface layer 68 and multi-layer thermal interface 80 may be appliedin a fabrication step that occurs after dielectric filler material 64 isapplied and cured, dielectric filler material 64 may be applied using anencapsulating or overmolding technique rather than a more costly andtime-consuming underfill process that is more likely to result in voids.Also, because the thermal interface is formed during the packagebuild-up process, rather than being provided as a prefabricatedcomponent, the dimensions and materials of thermal interface may betailored based on desired operating characteristics. Further, the use ofconducting shims 60, 120, 130, 142, and/or 152 provides the ability toaccount for semiconducting devices of varying heights.

While embodiments of the invention have been described as includingpower semiconductor devices used in high voltage power applications, oneskilled in the art will recognize that the techniques set forth hereinare equally applicable to low power applications and chip packages thatincorporate non-power semiconductor devices or semiconductor deviceshaving electrical connections that run to only a single side of thesemiconductor devices.

Therefore, according to one embodiment of the invention, a power overlay(POL) structure includes a POL sub-module. The POL sub-module includes adielectric layer and a semiconductor device having a top surfaceattached to the dielectric layer. The top surface of the semiconductordevice has at least one contact pad formed thereon. The POL sub-modulealso includes a metal interconnect structure that extends through thedielectric layer and is electrically coupled to the at least one contactpad of the semiconductor device. A conducting shim is coupled to abottom surface of the semiconductor device and a first side of a thermalinterface is coupled to the conducting shim. A heat sink is coupled to asecond side of the electrically insulating thermal interface.

According to another embodiment of the invention, a method of forming apower overlay (POL) structure includes providing a semiconductor device,affixing a first surface of the semiconductor device to a dielectriclayer, forming vias through the dielectric layer and forming a metalinterconnect structure extending through the vias in the dielectriclayer to electrically connect to the semiconductor device. The methodalso includes affixing a first surface of a conductive shim to a secondsurface of the semiconductor device and forming a thermal interface atopa second surface of the conductive shim. Further, the method includesthermally coupling a heat sink to the conductive shim absent a directbond copper (DBC) substrate positioned between the heat sink and theconductive shim.

According to yet another embodiment of the invention, a power overlay(POL) packaging structure includes a POL sub-module. The POL sub-moduleincludes a dielectric layer, a first semiconductor device attached tothe dielectric layer, and an interconnect structure electrically coupledto a first side of the first semiconductor device. The interconnectstructure extends through the dielectric layer to electrically connectto at least one contact pad on the first semiconductor device. A firstconducting shim has a bottom surface coupled to a second side of thefirst semiconductor device and a thermal interface coupled to a topsurface of the first conducting shim absent a direct bond copper (DBC)substrate positioned therebetween. A heat sink is directly coupled tothe thermal interface.

According to yet another embodiment of the invention, a semiconductordevice package includes a first semiconductor device, a secondsemiconductor device having a thickness that is greater than a thicknessof the first semiconductor device, and an insulating substrate coupledto first surfaces of the first and second semiconductor devices. Ametallization layer extends through the insulating substrate such that afirst surface of the metallization layer is coupled to the contact padsof the first and second semiconductor devices. A first conducting shimhaving a first side is coupled to the first semiconductor device via aconductive contact layer; a second conducting shim having a first sideis coupled to the first semiconductor device via the conductive contactlayer. The first conducting shim has a thickness that is greater than athickness of the second conducting shim and second sides of the firstand second conducting shims are co-planar.

According to yet another embodiment of the invention, a semiconductordevice package includes a dielectric layer having a plurality of viasformed therethrough and a semiconductor device having a first surfacecoupled to a top surface of the dielectric layer. The semiconductordevice package also includes a metal interconnect structure coupled to abottom surface of the dielectric layer. The metal interconnect structureextends through the plurality of vias of the dielectric layer to connectto the first surface of the semiconductor device. The semiconductordevice package also includes a conducting shim having a bottom surfacecoupled to a second surface of the semiconductor device and an organicthermal interface coupled to a top surface of the conducting shim absenta direct bond copper (DBC) substrate positioned between the organicthermal interface and the conducting shim.

While the invention has been described in detail in connection with onlya limited number of embodiments, it should be readily understood thatthe invention is not limited to such disclosed embodiments. Rather, theinvention can be modified to incorporate any number of variations,alterations, substitutions or equivalent arrangements not heretoforedescribed, but which are commensurate with the spirit and scope of theinvention. Additionally, while various embodiments of the invention havebeen described, it is to be understood that aspects of the invention mayinclude only some of the described embodiments. Accordingly, theinvention is not to be seen as limited by the foregoing description, butis only limited by the scope of the appended claims.

What is claimed is:
 1. A semiconductor device package comprising: afirst semiconductor device coupled to a first surface of a dielectriclayer; an interconnect layer coupled to a second surface of thedielectric layer, the interconnect layer extending through at least oneopening in the dielectric layer to connect to at least one contact padon a first surface of the first semiconductor device; a first conductivecontact layer disposed on a second surface of the first semiconductordevice; a first conductive shim coupled to the first semiconductordevice by way of the first conductive contact layer; and a firstlead-frame joined to the first conductive shim.
 2. The semiconductordevice package of claim 1 wherein the first lead-frame is joined to thefirst conductive shim by one of a solder, braze, and weld joint.
 3. Thesemiconductor device package of claim 1 wherein the first conductiveshim and the first lead-frame are fabricated from a common copper slab.4. The semiconductor device package of claim 1 further comprising: asecond semiconductor device having a first surface coupled to the firstsurface of the dielectric layer; a second conductive contact layerdisposed on a second surface of the second semiconductor device; asecond conductive shim coupled to the second semiconductor device by wayof the second conductive contact layer; and a second lead-frameextending outward from the second conductive shim.
 5. The semiconductordevice package of claim 4 further comprising a thermal interface coupledto a top surface of the first conductive shim and a top surface of thesecond conductive shim.
 6. The semiconductor device package of claim 4wherein a top surface of the first conductive shim and a top surface ofthe second conductive shim are co-planar.
 7. The semiconductor devicepackage of claim 6 wherein the first semiconductor device and the secondsemiconductor device differ in height.
 8. The semiconductor devicepackage of claim 1 further comprising a thermal interface disposed on atop surface of the first conductive shim, the thermal interfacecomprising a thermally conductive and electrically insulating material.9. The semiconductor device package of claim 8 further comprising afiller material disposed between the dielectric layer and the thermalinterface and surrounding the first semiconductor device.
 10. A methodfor manufacturing a semiconductor device package comprising: coupling afirst semiconductor device to a first side of a dielectric substrate;forming at least one opening through a thickness of the dielectricsubstrate; disposing an interconnect layer on a second side of thedielectric substrate and into the at least one opening to electricallycouple the interconnect layer to at least one contact pad on a firstsurface of the first semiconductor device; applying a first conductivecontact layer on a second surface of the first semiconductor device; andcoupling a first conductive shim to the first semiconductor device byway of the first conductive contact layer, the first conductive shimhaving a lead-frame joined thereto.
 11. The method of claim 10 furthercomprising coupling the first conductive shim to the first semiconductordevice with a solder layer.
 12. The method of claim 10 furthercomprising applying a filler material to surround the firstsemiconductor device, the first conductive contact layer, and at least aportion of the first conductive shim.
 13. The method of claim 10 furthercomprising patterning the interconnect layer to define a plurality ofmetal interconnects.
 14. The method of claim 10 further comprising:coupling a second semiconductor device to the first side of thedielectric substrate, the second semiconductor device thicker than thefirst semiconductor device; electrically coupling at least one contactpad on a first surface of the second semiconductor device to theinterconnect layer through at least another opening in the dielectricsubstrate; applying a second conductive contact layer on a secondsurface of the second semiconductor device; and coupling a secondconductive shim to the second semiconductor device by way of the secondconductive contact layer, the second conductive shim thinner than thefirst conductive shim.
 15. The method of claim 14 further comprisingapplying a thermal interface atop the first and second conductive shims,the thermal interface comprising one of a thermal grease, a thermaladhesive, and a thermal paste.
 16. The method of claim 14 furthercomprising sizing the first and second conductive shims such that thetop surfaces thereof are co-planar when coupled to the first and secondsemiconductor devices.
 17. A semiconductor device package comprising: aplurality of semiconductor devices disposed on a dielectric substrate;an interconnect layer extending through openings in the dielectricsubstrate to electrically couple with contact pads provided onrespective first surfaces of the plurality of semiconductor devices; aplurality of conductive shims positioned atop the plurality ofsemiconductor devices and electrically coupled to respective secondsurfaces thereof; and at least one lead-frame joined to at least one ofthe plurality of conductive shims.
 18. The semiconductor device packageof claim 17 wherein the plurality of semiconductor devices are ofdiffering thicknesses; wherein the plurality of conductive shims are ofdiffering thicknesses; and wherein respective top surfaces of theplurality of conductive shims are co-planar.
 19. The semiconductordevice package of claim 17 wherein the plurality of semiconductordevices comprises a first semiconductor device and a secondsemiconductor device, the second semiconductor device having a thicknessgreater than a thickness of the first semiconductor device; and whereinthe plurality of conductive shims comprise a first conductive shimcoupled to the first semiconductor device and a second conductive shimcoupled to the second semiconductor device, the first conductive shimhaving a thickness greater than a thickness of the second conductiveshim.
 20. The semiconductor device package of claim 17 furthercomprising a layer of thermally conductive and electrically insulatingmaterial extending across top surfaces of the plurality of conductiveshims.
 21. A semiconductor device package comprising: a dielectriclayer; at least one stacked assembly comprising: a semiconductor devicehaving a first surface coupled to the dielectric layer; and a conductiveshim stacked atop the semiconductor device and coupled thereto with aconductive material; and a metallization layer comprising at least onemetal interconnect extending through at least one opening in thedielectric layer and forming a direct metallic connection with at leastone contact pad on the first surface of the semiconductor device. 22.The semiconductor device package of claim 21 wherein the at least onestacked assembly comprises a plurality of stacked assemblies, eachcomprising a semiconductor device coupled to a conductive shim with aconductive material; wherein the top surfaces and the bottom surfaces ofthe plurality of stacked assemblies are co-planar; wherein thesemiconductor devices of the plurality of stacked assemblies are ofvarying heights; and wherein the conductive shims of the plurality ofstacked assemblies are of varying heights.
 23. The semiconductor devicepackage of claim 21 wherein the semiconductor device is coupled to thedielectric layer with an adhesive; and wherein the at least one metalinterconnect extends through the dielectric layer and the adhesive. 24.The semiconductor device package of claim 21 further comprising athermal interface applied to a top surface of the at least one stackedassembly, the thermal interface comprising a thermally conductive andelectrically insulating material.
 25. The semiconductor device packageof claim 21 wherein the conductive material comprises solder.
 26. Amethod of manufacturing a semiconductor device package comprising:coupling at least one semiconductor device to a first surface of adielectric layer with an adhesive; metalizing a second surface of thedielectric layer and at least one via in the dielectric layer and theadhesive to form an interconnection layer electrically coupled to atleast one contact pad on a first surface of the at least onesemiconductor device; positioning at least one conducting shim atop theat least one semiconductor device in a stacked arrangement; and couplingthe at least one conducting shim joined to the at least onesemiconductor device with a conductive material.
 27. The method of claim26 further comprising curing the adhesive to secure the at least onesemiconductor device to the dielectric layer.
 28. The method of claim 26further comprising forming the at least one via in the dielectric layerand the adhesive using one of a laser ablation, laser drilling, plasmaetching, photo-definition, and mechanical drilling process.
 29. Themethod of claim 26 wherein stacking the at least one conducting shimatop the at least one semiconductor device comprises stacking a firstconducting shim atop a first semiconductor device and stacking a secondconducting shim atop a second semiconductor device, the secondsemiconductor device differing in height from the first semiconductordevice.
 30. The method of claim 29 further comprising grinding at leastone of a back surface of the first conducting shim and a back surface ofthe second conducting shim such that the back surfaces of the first andsecond conducting shims are co-planar.
 31. The method of claim 26further comprising applying a layer of electrically conductive andthermally insulating material on a back surface of the at least oneconducting shim.